Title: Dorado: Scaling SmartNIC Session Tables on Commodity DDRs
Authors: Heng Yu (Tsinghua University); Kai Ren, Jiajun Liang, Baozeng Zhang (Tencent); Guozhi Lin (University of Chinese Academy of Sciences); Xinyi Zhang (CNIC CAS); Jian Wang, Jian Zhao (Tencent); Ziyue Zhai (University of Chinese Academy of Sciences); Liang Wang, Chao Pei (Tencent); Jilong Wang (Tsinghua University); Gaogang Xie (CNIC CAS); Ang Chen (University of Michigan); Congcong Miao (National University of Singapore)
Introduction
FPGA-based SmartNICs are increasingly used to accelerate cloud network functions because they can offload fast-path packet processing from host CPUs. However, as cloud services scale, the session tables maintained by these SmartNICs are becoming much larger. In the production workloads studied by the authors, session tables can contain up to 16 million entries while the dataplane must sustain 50 Mpps packet processing. Existing approaches typically rely on SRAM or HBM to provide sufficient memory performance, but SRAM has limited capacity and HBM is significantly more expensive to deploy across millions of SmartNICs. Cache-based designs can also suffer from unpredictable performance when the working set exceeds the cache capacity. This creates a fundamental tension between memory capacity, packet-processing performance, and hardware cost. Dorado addresses this problem by scaling SmartNIC session tables entirely on inexpensive commodity DDR memory while still targeting line-rate packet processing.
Key Idea and Contribution
The key idea of Dorado is that commodity DDR does not necessarily have to be slow if the entire hardware/software datapath is redesigned around its characteristics. The authors develop three complementary techniques.
First, they introduce a diffused session table, which restructures each session entry into separate Hash, Flow, and Stat tables and distributes them across multiple DDRs using a double-discrete mapping strategy. This reduces unnecessary memory transfers and spreads accesses across DDR banks and modules.
Second, they design a hybrid processing pipeline that combines packet processing and control-plane commands in a single pipeline. By decomposing the pipeline into fine-grained modules and using a mirrored read/write order together with asymmetric locking, Dorado reduces lock contention while maintaining operation atomicity and correctness.
Third, Dorado introduces adaptive processing speedup to address two major sources of pipeline stalls. The write-operation merger combines multiple updates from packets belonging to the same elephant flow, turning most of them into read-only operations and thereby reducing contention on the Stat table. The out-of-order scheduler decouples packet execution from packet arrival order and uses DDR response arrival as the scheduling signal, which reduces head-of-line blocking caused by out-of-order memory responses. Together, these mechanisms allow Dorado to extract much more useful performance from commodity DDR without adding a large cache or relying on expensive HBM.
Evaluation
Dorado is evaluated both on a hardware testbed and in a large production cloud environment. On the testbed, Dorado improves session-table access rates by 44%, achieves nearly 50 Mpps packet processing with a single pipeline, and reaches 14.93 Mpps for a single session after applying the write-operation merger. Compared with state-of-the-art systems such as Tiara and AccelNet, Dorado improves packet-processing performance by approximately 33%, even while using fewer hardware resources and no cache resources. Its throughput remains stable as the session-table size increases, and even under heavy control-command injection, packet-processing performance degrades only slightly.
The production results are particularly important. Dorado has been deployed on millions of servers and has processed traffic from billions of users for more than three years. It can support up to 16M session entries, achieve 50 Mpps line-rate processing, and reduce memory cost by approximately 80% compared with the HBM-based solution. This result is significant because it shows that careful architecture and data-structure co-design can make a low-cost commodity memory technology viable for high-performance SmartNIC dataplanes at massive cloud scale, rather than simply accepting the conventional trade-off between performance and memory cost.
Q&A
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Personal Thoughts
What I find most impressive about Dorado is that the paper does not solve the memory problem by simply introducing a faster memory technology. Instead, it starts from the characteristics and limitations of commodity DDR and then redesigns the session table, processing pipeline, and memory scheduling mechanism together. The three techniques are tightly connected: the new data layout makes DDR accesses more efficient, the pipeline decomposition enables concurrency with less locking overhead, and the adaptive scheduler hides memory latency and avoids stalls. This makes the contribution feel more like a complete system redesign than an isolated optimization.
Another aspect I particularly like is the combination of microarchitectural insight and large-scale production validation. The paper does not stop at a small FPGA prototype; it demonstrates that the system has been deployed for years in a real cloud environment. At the same time, I think there are still interesting questions worth exploring. For example, Dorado is carefully optimized for session-table workloads with relatively structured access patterns and specific DDR characteristics. It would be interesting to study how well the same design principles generalize to emerging memory technologies such as CXL-attached memory or next-generation SmartNIC memory systems. Another possible direction is whether the diffused-table and response-driven scheduling ideas can be generalized into a reusable hardware abstraction for other stateful network functions beyond the workloads evaluated in the paper.