Title : vPIFO: Virtualized Packet Scheduler for Programmable Hierarchical Scheduling in High-Speed Networks
Authors : Zhiyu Zhang, Shili Chen, Ruyi Yao, Ruoshi Sun, Hao Mei, Hao Wang, Zixuan Chen, Gaojian Fang (Fudan University); Yibo Fan (State Key Laboratory of ASIC and System, Fudan University); Wanxin Shi, Sen Liu, Yang Xu (Fudan University)
Scribe : Huan Shen (Xiamen University)
Introduction
The paper is about hardware programmable hierarchical scheduler in high-speed networks, specifically within the context of Multi-Tenant Data Centers (MTDCs). Existing hierarchical scheduling methods lack structural programmability to meet the diverse and dynamic scheduling needs. The paper proposes a PIFO virtualization solution where a single physical PIFO queue is virtualized to serve multiple logical PIFO nodes, enabling network operators and tenants to customize hierarchical scheduling algorithms according to their requirements.
Key idea and contribution
In Multi-Tenant Data Centers, different layers have different network performance goals, which necessitate the implementation of different hierarchical scheduling policies. Implementing a hierarchical scheduling policy requires a dedicated PIFO Tree. The key idea of the paper is the virtualization of a single physical PIFO to serve multiple logical PIFO nodes, allowing for the flexible instantiation of arbitrary PIFO Trees to enable programmable hierarchical scheduling.
The main challenges lie in virtualization support, resource allocation, and scheduling requirement specification. Based on the pipelined BMW-Tree, the paper designs a multiplexing physical PIFO to support virtualization, decoupling the computation and storage parts, allowing the storage data of multiple logical PIFO nodes to time-multiplex a single set of computational resources. The paper designs a hypervisor for efficient allocation, which mainly includes an operation FIFO queue for each PIFO instance to store operations and a dispatcher to distribute the operations to their corresponding RPUs for execution. The paper also provides a Scheduling Description Language (SDL) for users to describe scheduling requirements effortlessly.
Evaluation
The system is an integrated hardware and software solution. The paper evaluates the scheduling system on FPGA and conducts packet-level simulations using NS3. The results show that vPIFO can flexibly support hierarchical scheduling within the scale of 128 PIFO instances while achieving an impressive speed of 400 Gbps with 6 levels of hierarchical scheduling. The simulation results show that vPIFO can reduce the Flow Completion Time (FCT) by a factor of 10 compared to BMW-tree.
Q&A
Personal thoughts
The paper tackles the Programmable Hierarchical Scheduling problem, which is essential in modern Multi-Tenant Data Centers. However, the system only runs at up to 400Gbps, which cannot compare to network switch speeds (Tbps) and is therefore not practical in Data Centers.